Extended RISC-V soft core for the Basys3 FPGA — RV32IM + Zba + Zicsr/Zifencei/Zicntr on a 5-stage in-order pipeline with a bimodal branch predictor. Built on the TU Graz HaDes-V open educational ...

This repository contains the complete C++/Python source, configurations, and design documents for the current release. Video files are intentionally excluded.