This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed ...

Extended RISC-V soft core for the Basys3 FPGA — RV32IM + Zba + Zicsr/Zifencei/Zicntr on a 5-stage in-order pipeline with a bimodal branch predictor. Built on the TU Graz HaDes-V open educational ...